library ieee;
use ieee.std_logic_1164.all;

entity multiplier_tb is
	
end entity multiplier_tb;

architecture RTL of multiplier_tb is

    component multiplier is
    	port (
    		clk, reset, start, setMultiplicand, setMultiplier : in bit;
    		dataInExternal : in bit_vector(31 downto 0);
    		done : out bit;
    		product : out bit_vector(63 downto 0)
    	);
    end component;
	
	for all : multiplier use entity work.multiplier(Structural);
	
	signal clkIn, startIn, setMultiplicandIn, setMultiplierIn: bit := '0';
	signal resetIn : bit := '1';
	signal doneOut : bit;
	signal data : bit_vector(31 downto 0) := "00000000000000000000000000000000";
	signal productOut : bit_vector (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";

	
begin

	clkIn <= not clkIn after 50 ns;
	
	MULTI : multiplier port map (clkIn, resetIn, startIn, setMultiplicandIn, setMultiplierIn, data, doneOut, productOut);
	
	tb : PROCESS
		
	begin
	    
	    wait for 105 ns;
	    --change to input multiplier state
	    startIn <= '1';
	    resetIn <= '0';
	    
	    wait for 55 ns;
	    --Load data into the Shift register
	    --@TODO change this load from a text file
	    data <= "00000000000000000000000000000001";
	    
	    wait for 105 ns;
	    --Move the Multiplicand to the lower 32 bits of the shift register
	    startIn <= '0';
	    setMultiplicandIn <= '1';
	    
	    wait for 105 ns;
	    --change the data to be loaded in to the shift register
	    --@TODO change this to read from a text file
	    data <= "01111111111111111111111111111111";
	    
	    wait for 105 ns;
	    --change the state to start the multiplication
	    setMultiplierIn <= '1';
	    setMultiplicandIn <= '0';
	    
	    wait for 100 us;
	    
	    --Multiply: loop
    		  --exit Multiply when doneOut = '1';
    		  --wait for 50 ns;
    	 --end loop;
    	 wait;
	    	
	end PROCESS;
	

end architecture RTL;
